RUIN - Rapid Universal Interface

Medipix

Medipix2 and Medipix3 are collaborations between number of European Universities and Research Institutes. The aim of the Collaboration is to carry out the design and evalutation of the semiconductor pixel detectors called Medipix (or newly Timepix). The hybrid silicon pixel detector device Medipix was designed for imaging by single quantum counting in each pixel. The device consists of a pixelated sensor chip and a read-out chip containing the amplifier, discriminators and counter(s) for each pixel.

Pixels: 256 x 256
Pixel size: 55 x 55 mm2
Area: 1.5 x 1.5 cm2

Medipix - counting

Planar pixellated detector (Si, GaAs, CdTe) is bump-bonded to read-out chip.
Ionizing particle creates a charge in a sensitive volume.
The charge in each pixel is amplified and compared with a threshold.
Digital counter is incremented.

Medipix - counting

Medipix - data read-out

The serial readout uses a LVDS port to shift out all the matrix data. In readout mode the 14-bit shift register of each pixel is connected to the next one forming a 3584-bit shift register. Communication between the pixel matrix and the IO logic is carried out through the 256-bit FSR. The number of clocks needed in order to read one chip are 917512 (256x256x14+8). External clock have to be used to shift the data from pixel to pixel.

Medipix - data read-out

RUIN - Design strategy

RUIN - Block diagram

Schema

Data de-serialization

New interface design puts emphasis on:

Speed of data read-out. (maximum speed possibility of the Medipix serial read-out: currently 200 MHz)
Support for all chips of MPX family

Strategy :

Conecting with PC

USB2.0 - transfer rate of 480 Mb/s
1Gb/s Ethernet

Usage of the digital signal processor

High data throughput
High computational performance (up to 8000 mips), even sophisticated data processing can be done here (threshold equalization, flat field correction, cluster analysis, data compression …)
Built in management of large memory

Usage of the FPGA

Hardware de-serialization of the serial data - decrease a processor load
I/O - LVDS, CMOS
Flexibility – possibility to change functionality without need of hardware modification

Principle of data de-serialization:

Serial data from Medipix are not loaded directly to the signal processor but are first de-serialized

The serial data are shifted to fast shift registers at high frequency generated by PLL.
When the registers are filled up, the parallel data are loaded to the latch.
DSP reads the data from the latch via the data bus at lower frequency.

Individual chips of the multichip assembly (Medipix Quad) can be read out simultaneously (the 32-bit fast shift register can be divided into four parallel 8-bit segments). Each segment can be fed from a separate Medipix chip.